Floating-point Divider

Overview

High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard. Features a generic latency from 2 to 49 clock cycles.

Ideal for floating-point pipelines, arithmetic units and processors.

Key Features

  • 32-bit floating-point arithmetic
  • IEEE 754 compliant
  • High-speed fully pipelined architecture
  • Trade off latency vs. speed
  • FPGA clock rates of 300 MHz+
  • Low area footprint

Benefits

  • Technology independent soft IP Core
  • Suitable for FPGA, SoC and ASIC
  • Supplied as human-readable source code
  • One-time license fee with unlimited use
  • Field tested and market proven
  • Any custom modification on request

Block Diagram

Floating-point Divider Block Diagram

Deliverables

  • VHDL source-code (or Verilog on request)
  • Simulation test bench
  • Examples and scripts
  • Full pdf datasheet
  • One-to-one technical support
  • One years warranty and maintenance

Technical Specifications

Foundry, Node
All
Availability
Immediate
×
Semiconductor IP