FlexRay Controller IIP

Overview

FLEXRAY CONTROLLER interface provides full support for the two-wire FLEXRAY CONTROLLER synchronous serial interface, compatible with FLEXRAY specification. Through its FLEXRAY CONTROLLER compatibility,it provides a simple interface to a wide range of low-cost devices. FLEXRAY CONTROLLER IIP is proven in FPGA environment.The host interface of the FLEXRAY CONTROLLER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

FlexRay Controller IIP is supported natively in Verilog and VHDL

Key Features

Compliant with FLEXRAY 3.0.1 Specification.
Support Full Duplex of operations.
Complete FlexRay Transmitter/ Receiver functionality.
Supports cluster wakeup and startup.
Transmit and receive commands allow the user to transmit and receive FlexRay data.
Supports 2.5, 5 and 10 Mbit/s bitrate.
Support Bit alignment
All types of frame generation.

Static frames
Dynamic frames

Various kinds of Tx and Rx errors detection.

Syntax errors
Frame ID error (Frame ID = 0)
Header CRC error
CRC error
Over and undersize errors
Content errors
Cycle Count error
Frame ID error
Startup, Sync & Null frame errors w.r.t Dynamic segment
Startup & Sync frame errors w.r.t Static segment
Reception of Null frame

Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple interface allows easy connection to microprocessor/microcontroller devices.

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The FLEXRAY Controller interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases.
Lint, CDC, Synthesis, Simulation Scripts with waiver files.
IP-XACT RDL generated address map.
Firmware code and Linux driver package.
Documentation contains User's Guide and Release notes.

Technical Specifications

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