FireLink IEEE1394b Link Layer Controller

Overview

The synthesizable IEEE1394b Link Layer Controller Core, FireLink®, is based on the Link Layer Controller that has been used for several years in the FireSpy® analyzers produced by DapTechnology. The code is written in VHDL and reference designs are currently available for Xilinx and soon for Altera FPGAs. DapTechnology offers two packages, i.e. Basic and Extended with differnet features and functions.

Currently, the LLC provides the control for transmitting and receiving 1394 packet, including asynchronous packets, isochronous packets and Phy packets, at speeds up to 800Mb/s. Future enhancements will support S1600 and S3200 speeds. However, support for these speeds is pending the final PHY/Link interface standardization.

As a special option, the FireLink® LLC offers Firmware Support for the AS5643 (Mil1394) protocol. While current implementations require significant host SW support the FireLink can support this layer with significantly better timing as well as reduced host resource utilization. Typical examples of applications in aerospace & defense for the FireLink® would include command & control systems for space-based vehicles, missile platforms, and fighter aircraft, as well as its implementation in avionics & IFE platforms for business and commercial aircraft.

Key Features

  • IEEE 1394-1995, 1394a-2000 and 1394b-2002 compliant
  • Supports 100, 200, 400, and 800Mbps data transfer rates
    • Future releases will support S1600 and S3200
  • Supports Legacy and Beta packets RX/TX (depending on the connected PHY)
  • Supports all standard 1394 packet types
  • Optional Cycle Master capability
  • Maximum packet size 8KB (for Basic version & depending on buffer size)
  • Isochronous and Asynchronous packet filters
  • Automatic Acknowledge generation depending on Link Layer Controller state, packet type and available buffer size
  • All kinds of forced errors, including:
    • Header CRC error
    • Data CRC error
  • PHY clock optional asynchronous to host clock
  • Isochronous transmit port for up to 8 channels
  • Compatible with Texas Instruments Physical Layer Controllers

Technical Specifications

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Semiconductor IP