FIFO capable of working in Highly Noisy environment, giving silicon ultimate stability in electromagnetic noisy environment.

Overview

Key Features

• Key Design Feature -
• 1. Synthesizable, Technology Independent, Verilog IP Core.
• 2. Configurable Data Width and FIFO Depth.
• 3. Noise resistant Dual Asynchronous Clock Architecture.
• 4. Noise resistant Gray Encoded Read and Write Pointers.
• 5. Noise resistant Full and Empty Flag Generation.
• 6. Ready-Valid Handshake.
• 7. Compatible with AMBA-AXI, Altera-AvalonST, Xilinx Locak Link.
• 8. Output Register for improving timing.

Benefits

• Using this FIFO will increase system reliability. Following are the key benefits of using this FIFO -
• 1. withstand Highly Electro-magnetic noise.
• 2. withstand Abrupt temperature changes
• 3. withstand Changes in Voltages.
• 4. withstand Abrupt clock glitches.
• 5. Useful for High Bandwidth and Reliable applications.

Applications

• The strength of LOW is suitable for noisy environment like
• Motors, CARS, Electrical equipment within factories.
• Strength of MID will give users a much advantage over the LOW in terms of More noisy environment protection.
• A strength of HIGH is a masterpiece and will not fail even when a directed Hacking event is performed on the device.
• By placing this block in a SOC, one can ensures more reliable
• and robust Device.

Deliverables

• 1. RTL Code.
• 2. Integration Guide.
• 3. Documentation.
• 4. Technology Independent Synthesys script.
• 5. List of synchronization flops.

Technical Specifications