Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the FPGA built-in transceiver. It is a one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. It provides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY.
It has been designed to provide simplicity and flexibility along with highest throughput around 8.5Gbps. Avalon/AXI interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface
Overview
Key Features
- USB 3.1 Specific Features
- Supports SuperSpeed+ (SSP) and SuperSpeed (SS) modes
- Uses FPGA Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.1
- USB 2.0 Specific Features
- Supports High Speed (HS) and Full Speed (FS) modes
- Provides well-known ULPI interface to interact with external USB 2.0 PHY
- Ease of Use
- Ready to use component for Altera’s Qsys
- Simple FIFO interface to transfer data over non-control endpoint
- Automated timing constraints
- Flexibility
- Capable to support up to 31 endpoints (1 default control endpoint, 15 IN endpoints and 15 OUT endpoints)
- Allows to select number of buffers per endpoint based on the requirement
Benefits
- No need for external PHY for USB 3.1 Gen 1 and Gen 2 interface
- Uses in-built transceiver as PHY layer
- Requires less pins compared to external PHY
Block Diagram
Video
eUSB 3.1 Gen 2 Device Controller IP Core Performance on Arria10
This video showcase the performance achieved for the eUSB 3.1 Gen 2 Device Controller IP Core on Arria 10 GX development kit.
Applications
- Imaging Device
- Smart Phones
- External Hard Disk
- Machine Vision
- Data Center
Deliverables
- Encrypted IP Core with Perpetual License
- Reference Design
- Reference Documents
- Reference HAL drivers
- Reference Windows Application
- Windows Driver (object code)
Technical Specifications
Availability
Now
Related IPs
- USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
- USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- USB 3.1 Gen1 / Gen2 Device Controller IP
- PCI Express Gen 1/Gen 2 Phy
- LogiCORE IP Serial RapidIO Gen 2