IP Catalog > Interface IP > Interconnect IP > Ethernet IP > Ethernet Switch IP > ETHERNET Switch IIP

ETHERNET Switch IIP

Overview

Ethernet Switch core is a full-featured, easy-to-use, synthesizable design that supports various Ethernet IEEE standards. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet Switch IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses

ETHERNET Switch IIP is supported natively in Verilog and VHDL

Key Features

  • Compliant with IEEE Standard 802.3-2018 Specification
  • Supports Full-duplex and Half-duplex 10M/100M/1G Ethernet interfaces
  • Supports 10G/25G/50G/40G and 100G Ethernet interfaces
  • Supports MII/GMII/RGMII/QSGMII/USXGMII Physical Layer device (PHY) interfaces
  • Supports different data rate for each port
  • Supports Dynamic MAC Table with automatic MAC addresses learning and aging
  • Supports Static MAC Table
  • Supports Jumbo Frame Management
  • Supports Ethertype Based Switching
  • Supports Ingress Port Mirroring
  • Supports Broadcast/Multicast Storm protection
  • Supports Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)
  • Supports timing synchronization as per IEEE Standard 1588-2008(PTP) and IEEE Standard 802.1AS(GPTP)
  • Supports Multicast Frame Filtering
  • Supports Switching Portmask
  • Supports Port-based VLAN
  • Supports QoS - Priorities(PCP-802.1p,DSCP TOS, Ethertype)
  • Supports DSA (Distributed Switching Architecture) tagging
  • Supports MDIO, AXI4-Lite or CoE(Configuration-over-Ethernet) SOC interfaces
  • Supports RSTP (Software stack required)
  • Supports MRP (Software stack not required)
    • Ring Manager (MRM)
    • Ring Client (MRC)
  • Supports DLR (Software stack not required)
    • Beacon Based Node
    • Supervisor Node
  • Supports Preemption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
  • Supports Traffic Scheduling - IEEE Standard 802.1Qbv and IEEE Standard 802.1Qav
  • Supports class based flow control and class based FIFO to store each class, total 8 class - IEEE Standard 802.1Q
  • In house UNH compliance tested
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to Microprocessor/Microcontroller devices

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

ETHERNET Switch IIP Block Diagram

Deliverables

  • The Ethernet interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Technical Specifications

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