Ethernet Switch 1G

Overview

Comcores Ethernet Switch IP core is a highly configurable and size-optimized implementation of a non-blocking crossbar switch that allows continuous transfers between up to 16 ports Ethernet ports via 1 Gbps GMII interfaces. The switch supports MAC learning and implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking.

The switch supports up to 16 ports where each port provides GMII native interface for Ethernet PHY devices. The number of ports is configurable at compile time. Comcores Ethernet Switch IP core is a silicon agnostic implementation targeting both ASICs and FPGAs.

Key Features

Feature Rich
- Automatic MAC address learning and aging
- Support programmable static forwarding entries
- Full duplex Ethernet interfaces
- Supports VLAN
Highly Configurable
- Up to 16 ports configurable at compile time
- Configurable queuing behavior (round-robin, fair queuing)
- Supports Ethernet Multicast
Easy to use
- Easy integration with standard Xilinx AXI4 Lite control interface
- GMII interfaces for attaching to an external Physical Layer device (PHY)
- Can be used in managed or unmanaged implementations
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs

Benefits

Silicon Agnostic
Ultra Compact Size
Hardware proven
Modular design with no performance limitations
Smallest size Ethernet Switch available
Optimal balance between IP-size and maximum data throughput rate can be configured

Block Diagram

Applications

C-RAN Switching
Test Equipment Applications
Industrial networks

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Simple Testbed, Test case, Test Script
- Access to support system and direct support from Comcores Engineers
- Synopsys Lint and CDC

Technical Specifications

Maturity

Mature

Availability

Available

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