Vendor: SmartDV Technologies Category: Ethernet

ETHERNET CYCLIC FEC IIP

ETHERNET CYCLIC FEC core is compliant with IEEE Standard 802.3.2018 Ethernet specification.Through its compatibility, it provides…

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Overview

ETHERNET CYCLIC FEC core is compliant with IEEE Standard 802.3.2018 Ethernet specification.Through its compatibility, it provides a simple interface to a wide range of low-cost devices. ETHERNET CYCLIC FEC IIP is proven in FPGA environment.The host interface of the ETHERNET CYCLIC FEC can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.

ETHERNET CYCLIC FEC IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with ETHERNET specification.
  • Supports Full IEEE Standard 802.3.2018 Ethernet cyclic FEC functionality.
  • This FEC(Forward Error correction) methodology implements the (2112 , 2080) binary cyclic code is shortened from the cyclic Fire code (42987, 42955).
  • Supports FEC of 32 bits parity bits.
  • This FEC can correct up to 11-bit burst error.
  • Supports the pipelined mechanism for the error correction.

Block Diagram

ETHERNET CYCLIC FEC IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The ETHERNET CYCLIC FEC interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
ETHERNET CYCLIC FEC IIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about Ethernet IP cores

What is ETHERNET CYCLIC FEC IIP?

ETHERNET CYCLIC FEC IIP is a Ethernet IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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