Ethernet AVB Verification IP

Overview

The Ethernet AVB Verification IP is compliant with IEEE 802.3 and IEEE 1722 specifications. Ethernet Audio Video Bridging is an emerging IEEE 802.1 standard designed by Audio Video Bridging (AVB) group to provide a reliable, high quality of service and low latency solution for streaming media. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Ethernet AVB Verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.

Ethernet AVB Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Ethernet AVB Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports AVB Endpoint talker and/or listener functionality
Full support for IEEE 1722
Full support for IEEE 802.1BA
Full support for IEEE 802.1Qav
Full support for IEEE 802.1Qat
Full support for IEEE 802.1AS
Supports 1G
- Supports GMII
- Supports TBI (i.e Output of 8b/10b PCS)
- Supports SGMII as per specification 1.8
- Supports QSGMII as per specification 1.2
- Supports USGMII as per specification 3.0 (5G and 10G)
- Supports RGMII/RTBI as per specification 2.0
- Supports 1000Base-KX
- Supports 1GBASE-SX and 1GBASE-LX
- Supports clause 73 backplane auto-negotiation for 1000Base-KX
- Supports clause 37 auto-negotiation
- Supports SGMII auto-negotiation
- Supports QSGMII auto-negotiation
- Supports USGMII auto-negotiation and packets
- Supports full duplex and half duplex of operation
Supports 100M
- Supports MII
- Supports SMII as per specification 2.1
- Supports RMII as per specification 1.2
- Supports 100BASE-FX
AVB protocol can be run over other ethernet speeds also
Supports MDIO slave and master model as per Clause 22 and Clause 45
Glitch insertion and detection
Supports all types of TX and RX errors insertion/detection at each layer.
Comes with Tx BFM, Rx BFM, and Monitor
Monitor supports detection of all protocol violations
Supports Pause frame generation and detection
Built in coverage analysis
Callbacks in master and slave for various events
Status counters for various events in bus

Benefits

Faster testbench development and more complete verification of Ethernet-AVB designs
Easy to use command interface simplifies testbench control and configuration of TX and RX
Simplifies results analysis
Runs in every major simulation environment

Block Diagram

Deliverables

Complete regression suite (UNH) containing all the Ethernet-AVB testcases.
Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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