The M85230 is an enhanced version of the Mentor Graphics M85C30 serial communications controller. The enhancements include: a deeper Transmit FIFO (4bytes); a deeper Receive FIFO (8 bytes); a programmable FIFO level for interrupts and DMA requests; latching of Read registers during reads; and automatic forcing of TxD pin high in Mark Idle mode. The M85230 has two independent full-duplex channels which support asynchronous, bit synchronous (SDLC, HDLC and SDLC loop mode) and byte synchronous (MONOSYNC*, BISYNC*) communication modes. NRZ, NRZI and FM data encoding/decoding are supported. It is fully programmable through its 8-bit system interface. Two diagnostic modes - local loop-back and automatic echo - are offered.
Enhanced version of M85C30 Serial Communications Controller
Overview
Key Features
- Software compatible with the Zilog Z85230
- Supports both asynchronous and synchronous communication modes
- SDLC loop-mode supported
- NRZ, NRZI and FM encoding/decoding
- 4byte Transmit FIFO; 8 byte Receive FIFO
- Two independent full-duplex channels
- Digital phase-locked loop for each channel
- Baud rate generator for each channel
- Local loop-back and automatic echo modes
- Character counter and 10x19-bit frame status FIFO in SDLC mode
- Fully synthesisable
Deliverables
- Verilog source code
- VHDL source code
- Synthesis script for Design Compiler
- Verilog & VHDL testbenches
- Reference technology netlist
- Product Specification & User Guide
Technical Specifications
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