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Vendor:
Synopsys, Inc.
Category:
NPU
Enhanced Neural Processing Unit for safety providing 8,192 MACs/cycle of performance for AI applications
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
Overview
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of Advanced Driver Assistance Systems (ADAS) and autonomous vehicle systems that require artificial intelligence (AI) for vision, RADAR, LiDAR and / or sensor fusion.
The NPX6FS NPUs include state-of-the-art hardware safety features including diagnostic error injection, windowed watchdog timers, error classification, and software diagnostic tests as well as safety monitors and lockstep capabilities for safety-critical modules. The processors include dedicated safety mechanisms for ISO 26262 compliance and address the mixed criticality and virtualization requirements of next-generation zonal architectures.
Comprehensive safety documentation, including safety manuals, FMEDA and DFMEA reports, accelerate SoC-level functional safety assessments. These features enable designers to achieve high levels of fault coverage as required for ASIL certifications without a significant effect on performance, power or area compared to the non-ASIL Ready NPX6 NPUs.
The NPX6FS NPUs are fully programmable and combine the flexibility of software solutions with the high performance and low power consumption of dedicated hardware.
The NPX6FS NPUs are supported by the ASIL D Ready ARC MetaWare MX Development Toolkit for Safety to help simplify the development of ISO 26262-compliant software.
Key features
- Adds hardware safety features to NPX6 NPU, minimizing area and power impact
- Supports ISO 26262 automotive safety standard
- Supports CNNs, transformers, including generative AI, recommender networks, RNNs/LSTMs, etc
- IP targets ASIL B and ASIL D compliance to ISO 26262
- Optional software test libraries complement integrated hardware safety features to achieve ASIL B compliance
- Supported by MetaWare MX Development Toolkit for Safety with ASIL D Ready compiler and graph mapping tool
- Extensive safety documentation eases certification process
Block Diagram
dwc_arc_npx6_8kfs_npu block diagram
Specifications
Identity
Part Number
dwc_arc_npx6_8kfs_npu
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Synopsys, Inc.
HQ:
USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
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Frequently asked questions about NPU IP cores
What is Enhanced Neural Processing Unit for safety providing 8,192 MACs/cycle of performance for AI applications?
Enhanced Neural Processing Unit for safety providing 8,192 MACs/cycle of performance for AI applications is a NPU IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this NPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.