eDisplayPort v1.4 Receiver Controller IP Core

Overview

This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. It supports the eDP 1.4b specification and can be implemented in any technology, making it highly adaptable for various design needs. With a wide range of host bus interfaces, including AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone, or custom buses, it seamlessly integrates into any design architecture. Delivered in Verilog RTL, the eDP Receiver IP Core can be implemented in either ASIC or FPGA, offering flexibility in hardware choices. The IP has been validated using FPGA, ensuring its reliability and performance in real-world scenarios. The comprehensive package includes RTL code, test scripts, and a test environment for streamlined simulation. This eDisplayPort Rx IP Core is a feature-rich, user-friendly, and synthesizable design that empowers developers to effortlessly integrate it into their SoC or FPGA projects. With its support for eDP 1.4b, compatibility with various host bus interfaces, and flexible implementation options, it provides a robust solution for high-quality video and audio reception in electronic devices.

Key Features

Supports eDP 1.4b specification
Supports full eDP Receiver functionality
Supports multi lanes upto 4 lanes.
Supports main link, Aux link and Hot plug functionality.
Supports packing of all the video formats supported by the display port
Supports HPD based link training
Supports deskew in sink device mode
Supports scrambler as in Display port specification
Supports scrambler reset after every 512th symbols.
Supports RGB, YCBCR444, YCBCR422, YCBCR420, Y-Only and RAW color format.
Supports PSR (Panel Self Refresh) entry and exit.
Supports frame number identification in PSR.
Supports Selective update (partial frame update) during Panel Self Refresh (PSR)
Supports PSR2(Panel Self Refresh) as per spec eDPv1.4b
Supports Multi SST operation(MSO) •Two SST Links with one Lane each (two Lanes total), 2x1 •Two SST Links with two Lanes each (four Lanes total), 2x2 • Four SST Links with one Lane each (four Lanes total), 4x1
Supports Advanced Link Power Management to reduce wake latency
Supports GTC-based video timing synchronization
Supports Display stream compression as per spec eDPv1.4b
Supports PSR Secondary Data Packet.
Supports Display Backlight Control Using DPCD Registers.
Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces
Supports high-bandwidth Digital Content Protection System version1.3 (HDCP v1.3)
Supports high-bandwidth Digital Content Protection System version2.2 (HDCPv2.2) • Supports for HDCP2.2 with full authentication • Supports for HDCP2.2 with bypass the authentication
Supports high-bandwidth Digital Content Protection System version2.3 (HDCPv2.3)
Fully synthesizable
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Fully compliant, silicon-proven core
Comes with Verilog testbench and option to buy full advanced System Verilog Testbench
Support directly from engineer who designed the code
Based on RMM (Re Use Methodology Manual guidelines)
Supports all the Synthesis tools

Block Diagram

Deliverables

RTL design in Verilog.
Lint, CDC synthesis script with waiver files.
Lint, CDC synthesis reports.
IP-XACT RDL generated address map.
Firmware code and Linux driver package.
Technical documentation in greater detail.
Easy to use Verilog test environment with Verilog test cases.

Technical Specifications

Maturity

In Production

Availability

Immediately

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