The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines.
Further optimize the E2 Core for the smallest area using SiFive Core Designer.
E20 Smallest, most efficient RISC V Ccore
Overview
Key Features
- RISC-V ISA - RV32IMC
- Machine Mode only
- 2-stage pipeline
- System Port for external memory accesses
- Core Local Interrupt Controller (CLIC) with 32 interrupts
- Advanced debug with 4 hardware breakpoints/watchpoints
- 1.22/1.84 DMIPS/MHz (Legal/Best Effort)
- 2.51 CoreMark/MHz
Block Diagram
