DVB-S2X LDPC BCH Decoder and Encoder

Overview

The DVB-S2X LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design for better performance and efficiency as well as
robust service availability.

Key Features

Irregular parity check matrix
Layered Decoding
Minimum sum algorithm
Soft decision decoding
BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
ETSI EN 302 307-1 V1.4.1 (2014-11) compliant
Medium codeword length
Extra code rates for finer gradation
Adding 64, 128, 256 APSK
Very low SNR down to -10dB
Wideband support

Benefits

Improved performance
Improved efficiency w.r.t. Shannon’s limit
Finer gradation of code rate and SNR
Very high data rate
Maximum service availability at highest efficiency
Enables cross layer optimization

Applications

DVB-S2X

Deliverables

Synthesizable Verilog
System Model (Matlab)
Verilog Test Benches
Documentation

Technical Specifications

Maturity

silicon proven

Availability

immediately

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