Dual SATA Host controller on Virtex 5 FXT FPGA
Overview
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5 IP is compliant with Serial ATA II specification and signaling rate is 1.5Gbps and scalable 3Gbs. The LDS SATA HOST DUAL XF5 IP is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of 1.5Gbps speed selection and 75MHz in case of 3Gbs speed selection. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available.
Key Features
- Physical Layer features
- Detect OOB and COMWAKE
- Detect the K28.5 comma character and provides a 16 bit parallel output
- Power management mode handled by state machine (shared between Phy and Link layer)
- Provides error indication to upper layers
- 8b/10b encoding and decoding in Xilinx Virtex 5 GTX Macro
- Fixed Speed selected at reset 1.5Gbs or 3Gbs
- Link Layer features
- Scrambling of tx data and descrambling of rx data
- CRC 32 calculation and check from Xilinx Virtex 5 hard macro
- Report transmission status and error to Transport Layer
- Enable BIST loopback and pattern generation modes
- Auto inserted hold primitive to avoid FIFO overflow and underflow
- Partial and slumber power management modes
- The interface between the link layer and the transport layer is 32-bit wide
- Transport Layer features
- 48-bits sector address
- Programmed IO (PIO) and DMA modes
- Support BIST FIS transmission and reception
- Automatic error FIS retry capability
- Implement Shadow Registers and SATA SuperSet registers
- Simple synchronous CPU and DMA Interface for data transfers including DMA hold-off capability
- DMA interface can be connected easily to memory space or FIFOs
- Support DMA Abort primitive
Benefits
- Complete EDK project available.
Deliverables
- Netlist
- Source Code
- Documentation
Technical Specifications
Maturity
Good
Availability
now