Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k

Overview

Dual Port SRAM compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k

Reduce the die cost
Unique architecture optimizing the periphery area for outstanding area gain
Extend the battery life
Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
Dynamic power reduction thanks to segment partitioning
Data retention mode at 1.2 V +/-10%, 1.1 V +/-10%, 0.9 V +/-10% and 0.6 V (optional) to drastically divide the leakage compared to simple stand by mode
Make the integration easier
Wide flexibility for words and bits per word
Flexible segment partitioning (Selectable 1-4 segments) allow the user to choose the best optimization between area, speed & power for his application
Two completely independent Read/Write Ports which implements full Dual-Port (2RW) functionality
Embedded extinction&retention switchs (ERS optional)
Enable right on 1st pass design, the Dolphin integration quality
Complete mismatch validation of the memory architecture taking in account local and global dispersion
Extended validation for high coverage rate of the compiler

Maturity

Pre-silicon