Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

Overview

Key Features

• • Dual independent single link mode (can drive 2 separate displays with different resolution)
• • 1P8M layout structure based on SMIC 40nm Logic LL 1P10M Salicide 1.1V/2.5V process.
• • 1.1V/2.5V +/-10% supply voltage, -40/+125C
• • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
• • Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
• • Input clock detector (self reset when missing clock)
• • Spread-spectrum input clock support
• (can be used in SS systems)
• • Output Swing Control (2.5mA to 7mA programmable), PVT compensated
• • Input clock detector (self reset when missing clock)
• • Low leakage power-down mode <10uA
• • Core cell area : [contact us] (I/Os included)
• • Power consumption [contact us] @150Mhz
• • Built-in power pads with ESD protection.
• • Equivalent part : Thine’s THC63LVD1025

Benefits

• support full HDTV @120hz (3DTV)
• Lowest bounding pad count
• Low cost IP
• reliability
• highly adjustable
• customization for your own design

Deliverables

• Design kit includes :
• - LEF view and abstract gdsII
• - Verilog HDL behavioral model
• - Liberty (.lib) timing constraints for typical, worse and best corner case
• - Full Datasheet /Application Note with integration guidelines document
• - Silicon characterization report when available
• Tapeout kit includes the design kit plus plysical view:
• - gdsII
• - LVS netlist and report
• - DRC/ERC/ESD/ANT report

Technical Specifications