Dolphin Quad SPI Controller
Overview
Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave. The core operates in various data modes from 4 bits to 32 bits. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.
Key Features
- Dolphin Quad-SPI Controller supports:
- + Master only operation
- + Slave only operation
- + Master and slave operation
- + Clock synchronization
- + Programmable FIFO watermarks
- + Interrupt interface
Benefits
- Compliant with the following specifications:
- + AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- + AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- + AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- + AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Applications
- Communications, Data Processing, Industrial, Automotive
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Maturity
Pre Silicon
Availability
Yes
Related IPs
- Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features
- Dolphin SPI Controller
- AXI Quad SPI
- Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
- Quad SPI Controller
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support