Dolphin Octal SPI Controller
Overview
Dolphin Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices. The Controller and PHY IP connects to a system-on-chip (SoC) host through an AMBA® APB bus for the register interface and optional DMA peripheral interface.
Key Features
- Dolphin Octal-SPI Controller supports:
- - Master only operation
- - Slave only operation
- - Master and slave operation
- - Clock synchronization
- - Programmable FIFO watermarks
- - Interrupt interface
Benefits
- Compliant with the following specifications:
- - AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
- - AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
- - AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
- - AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0
Applications
- Communications, Data Processing, Industrial, Automotive
Deliverables
- Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- Synthesis and STA scripts
- User guide documents
- SV/UVM Verification suite with BFM
Technical Specifications
Maturity
Pre Silicon
Availability
Yes
Related IPs
- Host controller IP for controlling flash and other devices on the SPI bus: Quad SPI, Octal SPI, and xSPI
- Dolphin SPI Controller
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- AHB Octal SPI Controller with Execute in Place