UART DO-254 IP Core

Overview

The Universal Asynchronous Receiver/Transmitter (UART) is a hardware device that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as TIA (formerly EIA) RS-232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable. The electric signaling levels and methods (such as differential signaling etc.) are handled by a driver circuit external to the UART.

The UART IP Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.

Implementation Details

Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.

No constraints were added, so the results listed under the column “Maximum frequency of operation” are the worst case scenario (no multicycle, false paths, etc. defined).

The results are provided for an UART Core with the following configuration generics (see Table 1):

  • ‘g_ASYNC_INPUT’ – TRUE
  • ‘g_CLOCK_DIVIDER’ – 139
  • ‘g_DATA_WIDTH’ – 8
  • ‘g_PARITY_ENABLE’ – ‘1’
  • ‘g_ODD_PARITY’ – ‘0’
  • ‘g_2_STOP_BITS’ – ‘1’

and without TMR (Triple Module Redundancy), if TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the maximum ‘clk’ frequency.

ACTEL / MICROSEMI

FPGA Type Maximum ‘clk‘ Frequency Logic Modules (CORE)
ProASIC3

 

(A3P015 68QFN I Std)

132 MHz 163
IGLOO

 

(AGL030V5 100VQPF I Std)

127 MHz 163
Fusion

 

(AFS090 180QFN I Std)

132 MHz 163
Axcelerator

 

(RTAX250S 208CQFP Mil Std)

141 MHz SEQUENTIAL (R-cells): 63

 

COMB (C-cells): 74

ALTERA

FPGA Type Maximum ‘clk’ Frequency Flip-Flops ALUTs ALMs Logic Cells
MAX II

 

(EPM240F100I5)

127 MHz 57 83
Cyclone III

 

(EP3C5E144I7)

> 340 MHz 57 83
Stratix II

 

(EP2S60F484I4)

> 420 MHz 59 66 42
Stratix III

 

(EP3SE110F780I3)

> 550 MHz 57 63 41
Stratix IV

 

(EP4SGX70HF35C2)

> 670 MHz 58 64 41

XILINX

FPGA Type Maximum ‘clk‘ Frequency Flip-Flops 4-LUTs Slices Macrocells
CoolRunnerII

 

(XC2C128-6-TQ144)

126 MHz 57 58
Spartan3

 

(XC3S50-4PQ208)

189 MHz 56 91 53
Virtex2

 

(XC2V40-4FG256)

174 MHz 56 90 53
Virtex4

 

(XC4VLX15-12SF363)

> 460 MHz 56 92 53
Virtex5

 

(XC5VLX30-3FF324)

> 390 MHz 56 35

Key Features

  • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
  • Configurable baud rate, number of data bits, parity and stop bits.
  • Fully deterministic handshake interface that allows easy handling of reception/transmission requests
  • Single clock domain fully synchronous design
  • Interface to standard RS-232 drivers, so it can be used without modification in standard hardware
  • Simple interface to user’s logic
  • TMR coded for SEU immunity (optional)
  • Technology independent (can be synthesized to any FPGA/CPLD vendor)

Block Diagram

UART DO-254 IP Core Block Diagram

Technical Specifications

Foundry, Node
All
Maturity
Integrated and Flying in aircraft.
Availability
Immediate
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Semiconductor IP