The I2C Master IP Core implements an I2C Master fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+).
The Inter-Integrated Circuit (I2C) is a multi-master, multi-slave, single-ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). The I2C bus is typically used for attaching lower-speed peripheral ICs to processors and microcontrollers.
The I2C Master IP Core has been developed to DAL A according to the DO-254. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
Safe Core Devices provides two separate IP Cores, one for the I2C Master IP Core and one for the I2C Slave IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.
DO-254 I2C Master
Overview
Key Features
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+)
- Configurable data rate (100kHz, 400kHz or 1000kHz)
- Support for all Options (Multi-master, Synchronization, Arbitration, Clock stretching, 10-bit slave address, General Call address, Software Reset and START byte)
- Single clock domain fully synchronous design
- Simple interface to user’s logic
- TMR coded for SEU immunity (optional)
- Technology independent (can be synthesized to any FPGA/CPLD vendor)
Block Diagram
Technical Specifications
Foundry, Node
All
Maturity
Hardware Tested
Availability
Immediate