The DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supports 20Gbps UHBR20, 13.5Gbps UHBR13.5, 10Gbps UHBR10, 8.1Gbps HBR3, 5.4Gbps HBR2, 2.7Gbps HBR and 1.62Gbps RBR data rates. Additionally, the IP also includes the transceiver for the AUX channel.
DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC 12FFC, N/S orientation
Overview
Key Features
- Supports 1.62G to 20Gbps data rates and compact die area
- Supports x1, x2 and x4 lanes
- Supports post-cursor 1 FFE for Main Link transmitter
- Supports four swing levels for Main Link transmitter
- Supports four pre-emphasis levels for Main Link transmitter
- Supports 20-bit/40-bit (DP1.4), 32bit (DP2.1) databus width of parallel interface
- Supports PLL-alive mode
- Supports built-in internal loopback mode for testing
- Supports AUX channel feature
- Supports Wire-Bond or Flip-Chip packages
- Can be integrated with USB PHY to realize type-C DP alternate
Block Diagram
Technical Specifications
Foundry, Node
TSMC 12FFC
TSMC
Pre-Silicon:
12nm
Related IPs
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- DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC 28HPC+, N/S orientation
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