DisplayPort 1.4 IP-core

Overview

Introducing our DisplayPort 1.4 IP-core – the perfect solution for your DisplayPort needs!

This compact and easy-to-use IP-core is available as both source (DPTX) and sink (DPRX).

The solution comes also with a Video Toolbox (VTB) for various video processing tasks including a timing generator, a test pattern generator and video clock recovery.

A thin host driver and API allow easy integration and control of the IP-core.

The IP-core is supported by a wide range of FPGA devices including;
* AMD UltraScale+
* AMD Artix-7
* Intel Cyclone 10 GX
* Intel Arria 10 GX
* Lattice CertusPro-NX

The IP-core source code is available on our GitHub page for your convenience. You can customize and tailor the IP-core to your specific needs and requirements, ensuring that it integrates seamlessly with your system. This also adds trust to your product, knowing that you have complete access to the underlying code.

Key Features

Support for 1.62, 2.7, 5.4, and 8.1 Gbps link rates
Support for 1, 2, and 4 DP lanes
Native video and AXI stream video interfaces
Single Stream transport mode (SST)
Multi Stream transport mode (MST)
Dual and quad pixels per clock
8 & 10-bits video
RGB 4:4:4 & YUV 4:4:4 colorspaces

Benefits

Compact RTL footprint
Easy-to-use
Simple API
Thin host driver
Source code

Deliverables

RTL source code (SystemVerilog)

Technical Specifications

Availability

Now

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