Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP

Overview

Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2). Integrated 100-ohm termination resistors, a built-in equalizer with configurable analogue features, and common-mode biassing Terminator resistance, BGR voltage, regulator voltage, and CDR bandwidth Support 1.8V/0.9V power supplies for internal analogue signal monitoring and PLL testing.

Key Features

eDP version 1.4a / DP version 1.4 compliant transmitter
Supports HDCP1.4 and HDCP2.2(Optional)
Supports Forward Error Correction (Optional)
Consists of configurable (4/2/1) link channels and one AUX channe
Supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate (ie 2.16Gbps etc)
Supports main link operation with 1 or 2 or 4 lanes
Supports both Default and Enhanced Framing Mode
Supports SST mode
Supports video packet and audio packet (8ch max)
Supports both Normal and Alternate Scrambler Seed Reset
Supports E-EDID data reading via I2C-over-AUX transaction
Supports Video test pattern generator (compliant with DP link CTS v1.2)
Configuration registers programmable via AMBA interface
Silicon Proven in TSMC 40nm LP

Block Diagram

Deliverables

Verilog RTL or netlist source code of LINK controller.
Abstracted timing models for synthesis and STA
Timing constrains for synthesis and physical layout
Behavioral Verilog Model, simulation test bench, run control scripts, and test stimuli
Physical design database
Integration guidelines
Reference software sample code

Technical Specifications

Foundry, Node

TSMC 40LP

Maturity

In Production

Availability

Immediate

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