The ALTUS28TR is a silicon-proven, BiCMOS, highly integrated, mmWave, agile transceiver offering a versatile combination of high performance, low power consumption and configurability for target applications.
The ALTUS28TR is a direct conversion transceiver silicon IP, operating at frequencies between 24 - 33 GHz. The receiver front-end provides high sensitivity, linearity and wide gain control range distributed throughout the RX chain, providing much room for calibration and optimization. The transmitter front-end exhibits direct upconverter, variable gain driving amplifier and wide gain control range. An integrated power detector is also implemented for external monitoring and control of transmitted power. Both transmitter and receiver involve LO leakage compensation circuitry that can minimize LO leakage and DC offsets, respectively.
The LO signal at the input is expected to cover the range of 8 - 11 GHz and then multiplied internally to the carrier frequency. The baseband part of the transceiver consists of two (I/Q channel) fully differential low pass filters with adjustable cut-off and flexible calibration scheme. The transceiver size is 2.7 x 2.7 mm2 and has been packaged in a 34-ball chip scale package (CSP).
Direct conversion transceiver, operating in the Ka-band (24 - 33GHz)
Overview
Key Features
- Direct up/down conversion
- TX BB input freq. range: DC to 750 MHz
- TX/RX mmW freq. range: 24 GHz to 33 GHz
- LO frequency range: 8 GHz to 11 GHz
- Typical TX gain: 14 dB
- TX gain control range: 50 dB
- Typical RX gain: 60 dB - 80 dB, depending on filter BW
- RX gain control range: 90 dB
- TX saturation power: 13 dBm
- RX noise figure: 5.5 dB
- Input/output impedance ports: single-ended 50Ohm
- 4-wire SPI control
- DC power: 540 mW in RX, 500 mW in TX mode
- Package: 2.7 x 2.7 mm2, CSP package
Block Diagram
Applications
- 5G communication systems
- Satellite communications
- Fixed wireless access
- PtP/PtMP Ka-band communications
- RADAR systems
- TDD/FDD communication systems
Deliverables
- Evaluation Board
- Netlist
- Layout Exchange Format, .lib files
- GDSII
- Footprint (LEF)
- Testbenches (optional)
- Documentation
- Behavioural model (verilog/verilogA)
Technical Specifications
Maturity
Silicon Proven
Availability
Available
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