An interpolating filter chain, numerically controlled oscillator, and mixer comprise the DUC. A lowpass interpolator, halfband interpolator, CIC compensation interpolator, CIC interpolator, and CIC gain correction comprise the filter chain.
Because sample rates are lower at the beginning of the chain, the earlier filters can maximize resource use by sharing multipliers. The CIC compensation interpolator improves the spectral response by accounting for later CIC droop when interpolating by two. For cell search and master information block recovery, LTE receivers typically employ a sampling rate of 1.92 Msps.
DIGITAL UP CONVERSION (DUC)
Overview
Key Features
- 70 MHz IF, 2.5.8, & 22MHz BWs (3dB)
- 204.8 MHz DAC Sample Rate
- The modem provides a 25 kHz fine-tune step
- Receiver / Exciter minimum freq step = 0.5 MHz, settling time < 100 us to 100Hz
- Basebang samples are converted to 70 MHz “digital IF”
- Polyphase filter approach reduces required 204.8 Msps processing to the simple data transfer
- 208.8 Msps DAC sample rate required to reduce DAC sinx/x roll-off
- The final 2x interpolation process employs parallel FIR filters that process at a 1x rate
- As a result of the quarter-wave frequency shift, the number of filter taps is reduced by a factor of two
- Maintain 16 bits in/out of DDC
- Complex mixer functions should keep 18 bits at the input and truncate to 16 bits at the output
- DUC share a single DDS FPGA instantiation
- DUC shares the same FPGA filter structures
Block Diagram
Technical Specifications
Short description
DIGITAL UP CONVERSION (DUC)
Vendor
Vendor Name
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