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Differential Clock Receiver to CMOS on TSMC CLN3E

Overview

The Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, ranging from high speed communication to low power consumer applications.

The Receiver macro is implemented in Analog Bits’ proprietary architecture that uses core and IO devices at core voltage only. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates signal ESD structures and a power supply ESD structure.

Key Features

  • Differential clock receiver
  • Single-ended output to chip core
  • Wide Ranges of input frequencies for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Programmable termination
  • Built-in hysteresis
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption

Technical Specifications

Foundry, Node
TSMC CLN3E
TSMC
Pre-Silicon: 3nm
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