The Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, ranging from high speed communication to low power consumer applications.
The Receiver macro is implemented in Analog Bits’ proprietary architecture that uses core devices only. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates proprietary ESD structures, which is proven in several generations of processes.