Die-to-Memory (D2M) PHY

Overview

Block Diagram

Applications

• Chiplets connected on standard organic packages without large silicon interposers or silicon bridges but with interposer-like bandwidth/power/latency.
• SiP applications that benefit from up to at least four times the substrate area compared to the largest silicon interposer and thus a far higher number of chiplets in the package, resulting in major performance and power advantages.
• ASIC designs where a Network on Chip is split across two or more chiplets.
• Applications that benefit from placement flexibility to mix and match chiplets of different dimensions.
• Chiplet applications–such as HBM—where there must be physical separation between a hot ASIC and heat-sensitive dies.

Technical Specifications