Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)

Overview

The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The lowlatency, low-power, and compact PHY supports NRZ and PAM-4 signaling from 2.5G to 112G data rates and is compliant with the OIF CEI-112G and CEI-56G standards for extra- short reach (XSR) links. The XSR PHY offers flexible layout for maximum bandwidth per die-edge by allowing placement of the square macros along all edges of the die. It deploys 16-lane transmit and receive macros for optimized segmentation on the multiple dies. The robust DLL-based clock forwarded architecture enables high energy efficiency while supporting reliable links of up to 50 millimeters for large MCMs. The PHY enables multi-die connectivity over organic substrates, which helps reduce packaging costs without requiring advanced interposer-based packaging over shorter distances. The embedded bit error rate (BER) tester and nondestructive 2D eye monitor capability provide on-chip testability and visibility into channel performance. Besides the PMA and PMD, the PHY includes a raw-PCS to facilitate the interface with the on-chip network, regardless of the existing networking protocol. The XSR IP is combined with Synopsys’ comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models, and crosstalk analysis for fast and reliable integration into SoCs

Key Features

Offers leading performance, power, and area / beachfront per terabit
Includes 16 lanes of NRZ and PAM-4 transmitters or receivers
Targeting the OIF XSR standards: CEI-112G and CEI-56G
Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility
Physical Medium Dependent (PMD) soft-layer includes power sequencing and calibration engines
Implements RX scope and PRBS and pattern generator, matcher and error counter for BERT testing
Non-destructive 2D eye monitor capability can be performed during mission-mode operation
Shared PLLs allow maximum energy efficiency
Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal path

Benefits

16-lane TX and RX square macros for placement in any edge of the die
Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
Implements NRZ and PAM-4 signaling
Meets the performance, efficiency and reliability requirements of die-to-die interconnects
Robust DLL-based, clock forwarded architecture minimizes complexity and power dissipation
Linear equalization and T-Coils in RX and TX allow compliance to XSR links up to 50mm for large MCM designs
Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
Targeting the OIF CEI-112G and CEI- 56G standards for XSR links

Applications

Hyperscale data center
Enterprise and campus networks
Cloud computing/networking
Service provider networks
Artificial intelligence and machine learning

Deliverables

Verilog models and test bench
Protocol-specific test bench
Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
GDSII
IP-XACT XML files with register details
ATPG models
IBIS-AMI models
Documentation

Technical Specifications

Foundry, Node

TSMC 12nm, N7, N6, N5 - FFC, FF

Maturity

Available on request

Availability

Available

TSMC

Pre-Silicon: 5nm , 6nm , 7nm , 12nm

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