DDR5 PHY in TSMC (N3E, N5)

Overview

Key Features

• Low latency, small area, low power
• Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
• Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
• DFI 5.0 compliant interface to the memory controller
• I/Os include receiver decision feedback equalization (DFE)
• PHY independent, firmware-based training using an embedded calibration processor
• Can be trained for up to four distinct states/frequencies to permit fast frequency changes between the four frequencies
• Three inactive idle states:
• Voltage and temperature compensated delay lines used for:
• Supports the following training features:
• Programmable Read/Write Preamble
• Includes a low-jitter PLL for both PHY clock generation and SDRAM clock generation
• Supports PHYs on any side of the die and L-shaped PHYs that go around the die-corner
• Includes the PHY Utility Block (PUB)
• At-speed loopback testing on both the address and data channels
• Delay line BIST and MUX-scan ATPG (stuck-at SCAN)
• Firmware-based DDR5/4 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and host receivers

Benefits

• Supports JEDEC standard DDR5 and DDR4 SDRAMs
• High-performance DDR PHY supporting data rates up to 8400 Mbps
• PHY independent, firmware-based training using an embedded calibration processor
• Supports up to 4 trained states/frequencies with <3us switching time
• I/O receiver decision feedback equalization
• VT compensated delay lines for DQS centering, read/write 1D (DDR4) and 2D training (DDR5), and per-bit deskew on both read and write data paths
• DFI 5.0-compliant controller interface
• Designed for rapid integration with Synopsys memory controller for a complete DDR interface solution

Applications

• Data centers (networking and storage)
• Servers
• Artificial intelligence/machine learning/ deep learning
• High-performance computing
• Digital home
• Digital office

Deliverables

• Executable .run installation file which includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
• PUB includes Verilog code, Synthesis/ STA constraints and scripts, sample verification environment, and data book
• Implementation Guide, Application notes, and quick start manuals
• Firmware for training, ATE test and diagnostics
• DDR PHY compiler
• Support for PHY emulation
• Optional deliverables include:
• Signal integrity consulting services
• PHY hardening consulting services
• Subsystems consulting services
• IP Prototyping kit for FPGA-based prototyping

Technical Specifications