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DDR5 NVRAM Memory Model

Overview

DDR5 NVRAM Memory Model provides an smart way to verify the DDR5 NVRAM component of a SOC or a ASIC. The SmartDV's DDR5 NVRAM memory model is fully compliant with standard DDR5 NVRAM Specification and provides the following features. Better than Denali Memory Models.

DDR5 NVRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR5 NVRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports DDR5 NVRAM memory devices from all leading vendors.
  • Supports 100% of DDR5 NVRAM protocol standard JESD79-5 (Draft).
  • Supports all the DDR5 NVRAM commands as per the specs.
  • Supports up to 1 TB device density.
  • Supports the following devices.
    • X4
    • X8
    • X16
  • Supports all speed grades as per specification.
  • Supports for Write Pattern command.
  • Supports for CA, CS and Read Preamble training modes.
  • Supports for Read training pattern.
  • Supports for Write leveling training mode.
  • Supports Programmable Write latency and Read latency.
  • Supports Programmable Preamble, Postamble and Interamble.
  • Supports Programmable burst lengths: 8, 16, 32.
  • Supports Sequential burst type and Burst order.
  • Supports for 2N mode.
  • Supports for all mode registers programming.
  • Supports for Write data mask.
  • Supports CRC for Write and Read operations.
  • Supports for DLL features.
  • Checks for following
    • Check-points include power up, initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Supports for Self Refresh and Power down operation.
  • Supports for Maximum power saving mode.
  • Supports for Post Package Repair (PPR).
  • Supports for Loop back concepts.
  • Supports for Row Extension Command
  • Supports for Per DRAM Addressability.
  • Supports for Multipurpose Command (MPC).
  • Supports for VrefCA command.
  • Supports for ZQ calibration.
  • Supports for CA Vref and DQ Vref training.
  • Supports for input clock stop and frequency change.
  • Supports for On-Die Termination (ODT).
  • Supports for Connectivity Test (CT) mode.
  • Supports for all timing delay ranges in one model: min, typical and max.
  • Protocol checker fully compliant with DDR5 NVRAM Specification JESD79-5 (Draft).
  • Constantly monitors DDR5 NVRAM behavior during simulation.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of DDR5 NVRAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

DDR5 NVRAM Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the DDR5 NVRAM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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