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DDR4 Memory Model

Overview

DDR4 Memory Model provides an smart way to verify the DDR4 component of a SOC or a ASIC. The SmartDV's DDR4 memory model is fully compliant with standard DDR4 Specification and provides the following features. Better than Denali Memory Models.

DDR4 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR4 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports DDR4 memory devices from all leading vendors.
  • Supports 100% of DDR4 protocol standard JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD79-4Cand JESD79-4D(Draft).
  • Supports all the DDR4 commands as per the specs.
  • Supports up to 16GB device density.
  • Supports X4,X8,X16 and X32 devices.
  • Supports all speed grades as per specification.
  • Quickly validates the implementation of the DDR4 standard JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD79-4C and JESD79-4D(Draft).
  • Supports On-the-fly protocol and data checking.
  • Supports Programmable Write latency and Read latency.
  • Supports Programmable burst lengths: 4,8.
  • Supports Programmable Preamble.
  • Supports Read preamble training.
  • Supports the following burst types.
    • Sequential
    • Interleave
  • Supports burst order.
  • Checks for following
    • Check-points include power up, initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Supports all mode register programming.
  • Supports Data Mask and Data Bus Inversion (DBI).
  • Supports write leveling for calibrations and ZQ Calibration commands.
  • Supports Fine Granularity Refresh Mode.
  • Supports Multipurpose Register.
  • Supports DQ Vref training.
  • Supports CRC for Write Operations.
  • Supports DLL features.
  • Supports Command Address Parity features.
  • Supports Post Package Repair (PPR).
  • Supports Control Gear down mode and CAL Mode Operation.
  • Supports Per DRAM Addressability.
  • Supports Connectivity Test (CT) mode.
  • Supports MBIST PPR.
  • Supports both Synchronous and Asynchronous On-Die Termination modes.
  • Supports Power Down features and Maximum Power Saving mode.
  • Supports input clock stop and frequency change.
  • Protocol checker fully compliant with DDR4 Specification JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD79-4C and JESD79-4D(Draft).
  • Constantly monitors DDR4 behavior during simulation.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of DDR4 designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

DDR4 Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the DDR4 testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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