DDR4 Controller
Overview
The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cost components to dense 128GB RDIMMs.
Key Features
- Component support for interface width of 8 to 80 bits (RDIMM, UDIMM, and SODIMM support)
- 128 GB density device support
- x4, x8, and x16 device support
- 8:1 DQ:DQS ratio support for x8 and x16 devices
- 4:1 DQ:DQS ratio support for x4 devices
- Dual slot support for DDR4 DIMMs
- 8-word burst support
- Support for 9 to 24 cycles of column-address strobe (CAS) latency (CL)
- Self-Refresh and Save-Restore
- ODT / DBI support
- Support for 9 to 18 cycles of CAS write latency
- Write leveling support for DDR4 (fly-by routing topology required component designs)
- JEDEC-compliant DDR4 initialization support
- Source code delivery in Verilog
- 4:1 memory to FPGA logic interface clock ratio
- Open, closed, and transaction based pre-charge controller policy
- Interface calibration and training information available through the Vivado hardware manager
Technical Specifications
Related IPs
- DDR4 Controller IP
- DDR Controller supporting DDR5 and DDR4
- DDR Controller supporting DDR5 and DDR4 with a CHI interface
- DDR Controller supporting DDR5 and DDR4 with a CHI interface and Advanced Feature Package
- DDR Controller supporting DDR5 and DDR4 with Advanced Features Package
- DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2