DDR4 Controller
Overview
The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cost components to dense 128GB RDIMMs.
Key Features
- Component support for interface width of 8 to 80 bits (RDIMM, UDIMM, and SODIMM support)
- 128 GB density device support
- x4, x8, and x16 device support
- 8:1 DQ:DQS ratio support for x8 and x16 devices
- 4:1 DQ:DQS ratio support for x4 devices
- Dual slot support for DDR4 DIMMs
- 8-word burst support
- Support for 9 to 24 cycles of column-address strobe (CAS) latency (CL)
- Self-Refresh and Save-Restore
- ODT / DBI support
- Support for 9 to 18 cycles of CAS write latency
- Write leveling support for DDR4 (fly-by routing topology required component designs)
- JEDEC-compliant DDR4 initialization support
- Source code delivery in Verilog
- 4:1 memory to FPGA logic interface clock ratio
- Open, closed, and transaction based pre-charge controller policy
- Interface calibration and training information available through the Vivado hardware manager
Technical Specifications
Related IPs
- ONFI 3.2 NAND Flash Controller
- LPDDR2 / LPDDR3 / DDR3 / DDR3L / DDR3U / DDR4 Combo I/O Pad Set
- SATA Controller IP Core
- JESD204B Controller IP
- Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process.
- Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.