DDR4 3DS Synthesizable Transactor

Overview

Key Features

• Supports 100% of DDR4 3DS protocol standard JESD79-4-1, JESD79-4-1A and JESD79-4-1B
• Supports all the DDR4 3DS commands as per the specs
• Supports up to 16 GB device density
• Supports X4 and X8 devices types
• Supports all speed grades as per specification
• Supports on the fly protocol and data checking
• Supports programmable write latency and read latency
• Supports programmable burst length :4, 8
• Supports following burst type:
  • Sequential
  • Interleave
• Supports burst order
• Checks for following:
  • Check-points include power on, initialization and power off rules
  • State based rules, active command rules
  • Read/Write command rules etc
  • All timing violations
• Supports all mode registers programming
• Supports write leveling for calibrations and ZQ Calibration commands
• Supports CRC for Write Operations
• Supports DLL features
• Supports Command Address Parity features
• Supports Post Package Repair (PPR)
• Supports Control Gear down mode Operation
• Supports Per DRAM Addressability
• Supports Connectivity Test (CT) mode
• Supports both Synchronous and Asynchronous On-Die Termination modes
• Supports Power Down features and Maximum Power Saving mode
• Supports all types of timing and protocol violation detection
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the DDR4 3DS testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications