DDR3_DDR4 IO Pad Set
Overview
The DDR3 / DDR4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended and differential signaling for DDR3 and DDR4 applications. Also included is a full complement of power, corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Key Features
- Full DDR4 capability
- Data rates – 1600 MT/s, 1866 MT/s, 2133 MT/s, 2400 MT/s
- Full DDR3 / DDR3L / DDR3U capability
- Data rates – 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, 2133 MT/s
- ESD Protection:
- JEDEC compliant
- 2KV ESD Human Body Model (HBM)
- 200 V ESD Machine Model (MM)
- 500 V ESD Charge Device Model (CDM)
- Latch-up Immunity:
- JEDEC compliant
- Tested to I-Test criteria of ± 100mA @ 125°C
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES 28nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
In Production:
28nm
HPP
,
28nm
SLP
Silicon Proven: 28nm HPP , 28nm SLP
Silicon Proven: 28nm HPP , 28nm SLP
UMC
Silicon Proven:
55nm