The impedance programmable I/O buffer provides a high-speed physical interface solution to support the increasing bandwidths demanded by today’s high-performance DDR3/DDR3L applications. The I/O buffer delivers performance up to 1066MHz (2133Mbps data rate), and serves as the integral link between the memory controller / PHY interface and the latest high-speed DDR3/DDR3L memory devices.
Electrical Properties Parameter Min Typ Max Units IO Supply Voltage VDDQ (DDR3 mode) 1.425 1.5 1.575 V IO Supply Voltage VDDQ (DDR3L mode) 1.283 1.35 1.418 V Core Supply Voltage VDD 0.81 0.9 0.99 V Temperature 0 25 125 C AC Performance (DDR3 mode) 1066 MHz Data Rate (DDR3 mode ) 2133 Mbps AC Performance (DDR3L mode) 800 MHz Data Rate (DDR3L mode ) 1600 Mbps Note: All performance specifications are subject to package and topology Deliverables and EDA Design Views Back-end Design Views (with License Front-end Design Views (with NDA) Agreement Verilog Model GDSII stream file Synopsys (LIB) CDL/Spice netlist Footprint (LEF) Application Notes inclusive of design Datasheet (PDF) integration guidelines (PDF) Extended Options • DDR2 compatibility • 2.5V IO oxide • Non point-to-point, multiple-load topologies • Peripheral IO ring construction