IP Catalog > Peripheral IP > Memory Controller & PHY IP > SDRAM Controller IP > DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4

DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4

Overview

DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.

The DDR SDRAM Controller is a parameterized core giving user the flexibility for modifying the data widths, burst transfer rates, and CAS latency settings of the design. In addition, the DDR core supports intelligent bank management, which is done by maintaining a database of "all banks activated" and the "rows activated" in each bank. With this information, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write commands issued to the DDR SDRAM.

Key Features

  • Performance of Greater than 100MHz (200 DDR)
  • Interfaces to JEDEC Standard DDR SDRAMs
  • Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits
  • Supports up to 8 External Memory Banks
  • Programmable Burst Lengths of 2, 4, or 8
  • Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0
  • Byte-level Writing Supported
  • Increased Throughput Using Command Pipelining and Bank Management
  • Supports Power-down and Self Refresh Modes
  • Automatic Initialization
  • Automatic Refresh During Nomal and Power-down Modes
  • Timing and Settings Parameters Implemented as Programmable Registers
  • Bus Interfaces to PCI Target, PowerPC and AMBA (AHB) Buses Available
  • Complete Synchronous Implementation

Block Diagram

DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4 Block Diagram

Technical Specifications

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