The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR SDRAM. The memory controller provides a generic command interface to the user's application. This interface reduces the effort to integrate the module with the remainder of the application and minimizes the need to deal with the DDR SDRAM command interface. The timing parameters for the memory can be set through the signals that are input to the core as part of the configuration interface. This enables switching between different memory devices and modification of timing parameters to suit the application using the same netlist.
Hardware Demo
A hardware demonstration bitstream for this IP core is available for use with the LatticeEC Advanced Evaluation Board. The bitstream, and a complete description of its operation is available for download by clicking the "Design Files" link in the resource box on this page.
DDR SDRAM Controller - Pipelined
Overview
Key Features
- Interfaces to industry standard DDR SDRAM devices and modules
- High-performance DDR 400/333/266/200/133 operation for LatticeECP3, LatticeECP2/M, LatticeECP2/MS and LatticeSC/M devices; DDR 333/266/200/133 operation for LatticeECP/EC devices; and DDR 266/200/133 operation for LatticeXP devices
- Programmable burst lengths of 2, 4 or 8 for DDR
- Programmable CAS latency of 2 or 3 cycles for DDR
- Intelligent bank management to optimize performance by minimizing ACTIVE commands
- Supports all JEDEC standard DDR commands
- Two-stage command pipeline to improve throughput
- Supports both registered and unbuffered DIMM
- Command burst function with dynamic burst size control
- Supports all common memory configurations
- SDRAM data path widths of 8, 16, 24, 32, 40, 48, 56, 64 and 72 bits
- Variable address widths for different memory devices
- Up to eight (DDR) chip selects for multiple SO/DIMM support
- Programmable memory timing parameters
- Byte-level writing through data mask signals
Block Diagram
Technical Specifications
Related IPs
- DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
- DDR SDRAM Controller
- DDR SDRAM Controller
- DDR2 SDRAM Controller - Pipelined
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- DDR SDRAM Controller supporting Altmemphy