How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Lattice Semiconductor Corp.
Category:
DDR
DDR/DDR2 SDRAM Controller MACO Core
The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that in…
Overview
The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that interfaces with industry standard DDR/DDR2 SDRAM devices and modules. This IP core is an IPexpress configurable core that provides the flexibility for modifying data widths, burst transfer rates, and CAS latency settings in a design. It provides a simple command interface for application logic. The controller can be configured to function as a DDR only or DDR2 memory controller.
This proven DDR/DDR2 core is optimized utilizing MACO ASIC gates in the LatticeSCM devices, resulting in fast, small cores that utilize the latest architecture to its fullest.
Note the RLDRAM IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.
Software Requirements
* ispLEVER version 7.1 or later
* MACO design kit
* MACO license file
This proven DDR/DDR2 core is optimized utilizing MACO ASIC gates in the LatticeSCM devices, resulting in fast, small cores that utilize the latest architecture to its fullest.
Note the RLDRAM IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.
Software Requirements
* ispLEVER version 7.1 or later
* MACO design kit
* MACO license file
Key features
- ispLEVER version 7.1 or later
- MACO design kit
- MACO license file
Block Diagram
DDRSDRAMControllerMACO block diagram
Specifications
Identity
Part Number
DDRSDRAMControllerMACO
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Lattice Semiconductor Corp.
HQ:
USA
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices ( PLD), including Field Programmable Gate Arrays ( FPGA), Complex Programmable Logic Devices ( CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.
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Frequently asked questions about DDR Interface IP
What is DDR/DDR2 SDRAM Controller MACO Core?
DDR/DDR2 SDRAM Controller MACO Core is a DDR IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.