Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4, DDR3/3L, DDR2, LPDDR5X/5, LPDDR4/4X, LPDDR3, LPDDR2, HBM3, HBM2E and HBM2 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the silicon-proven Synopsys DDR Memory Interface IP products include a choice of scalable digital controllers with Inline Memory Encryption (IME) Security Module, an integrated hard macro or configurable PHY delivering memory system performance of up to 8.5Gbps, and verification IP.
Synopsys' DDR and LPDDR PHYs are supportd by Synopsys' unique Synopsys DDR PHY Compiler for determining the area and power of a customer-specific configuration.
Synopsys DDR5/4, LPDDR5X/5/4/4X Controllers, and Enhanced Universal DDR Memory and Protocol Controller IP feature a DFI-compliant interface, low latency and low gate count while offering high bandwidth. Optional market-specific features like AMBA CHI, AXI/4 AXI Quality of Service (QoS) and advanced Reliability, Availability and Serviceability (RAS) features allow you to match the area and capabilities of the controllers to your needs. The Synopsys Inline Memory Encryption (IME) Security Module seamlessly integrates with Synopsys DDR and LPDDR controllers to provide confidentiality and data protection.
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Overview
Key Features
- Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
- uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
- LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
- Best in class performance with unique features such as QoS based scheduling and dual-channel support
- Offers several RAS features, such as Sideband ECC, Inline ECC, Command/Address Parity, etc., where supported by the DRAM protocol
- In-line ECC function provides error correction in systems that cannot use a sideband ECC
- LPDDR5/4/4X controller and uMCTL2 have an automotive license option, which has been designed with automotive safety features and includes ISO 26262 Work Products
Benefits
- #1 supplier of DDR interface IP (IPnest 2017)
- Comprehensive DDR IP solution includes protocol and memory controllers and PHY IP
- Products support various combinations of DDR5, DDR4, DDR3/3L, DDR2, LPDDR5, LPDDR4/4X, LPDDR3, LPDDR2, and LPDDR standards
- Each solution supports at least two generations of DDR standards (for example, DDR5 and DDR4)
Technical Specifications
Maturity
Available on request
Availability
Available
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