Controller for CXL

Overview

Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications

The Controller IP for CXL addresses a wide range of high-bandwidth and low-latency requirements for a broad spectrum of applications, including high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), storage solutions, accelerators, and memory expanders.

Key Features

The Controller IP for CXL provides the logic required to integrate a root-port (RP), end-point (EP), or dual-mode (DM) controller into any system on chip (SoC), and supports CXL 3.1, CXL 2.0 and CXL 1.1
Designed for lowest latency at the highest bandwidth possible and with a rich set of client interfaces available, the Cadence Controller IP for CXL allows superior flexibility for all three device types in the CXL specification
The Controller IP for CXL has been robustly verified with lead OEM partners in pre-silicon, and the Cadence subsystem test chips for PCIe and CXL include a CXL controller

Benefits

High Performance, Low Latency: Benchmarked at 95% of theoretical performance, superscalar design for high throughput and low latency
Application Optimized: IP features optimized for key applications like storage, managed memories, and AI/ML accelerators, configured to your specific needs with minimal gate count
Ease of Use: Fully verified pre-integrated IP delivery, with firmware and testbenches for rapid bring-up

Block Diagram

Deliverables

Clean, readable, synthesizable RTL Verilog files
Verification testbench example with integrated stimulus and monitors
Comprehensive user guide
Register descriptions
Synthesis scripts

Technical Specifications

Maturity

Silicon Proven

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