CXL 3.0 Integrity and Data Encryption Security Module

Overview

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiring high performance, heterogeneous computing for data-intensive workloads. The Synopsys CXL 3.0 Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity and replay protection for flow control units (FLITs) in the case of CXL.cache and CXL.mem protocols, and for FLITs and Transaction Layer Packets (TLP) in the case of CXL.io. The Security Module implements the IDE specification as defined for CXL 3.0 which also references PCI Express 6.0 IDE specification for the CXL.io protocol. The Synopsys CXL 3.0 IDE Security Module integrates seamlessly with the Synopsys CXL controllers to accelerate SoC integration

Benefits

  • Support for CXL 3.0 IDE specification for CXL.cache/mem
  • Support for PCIe 6.0 IDE specification for CXL.io
  • High-performance AES-GCM based packet encryption, decryption, authentication
  • FIPS 140-3 certification support
  • TDISP support for CXL.io
  • Seamless integration with Synopsys Controller IP –FLIT interfacing for CXL.cache/mem –FLIT/TLP interfacing for CXL.io –Efficient sync/fail/status messaging
  • Customer configurable –Aligns with Synopsys CXL 3.0 controller configuration options –Data bus widths: 128, 256, 512, 1024 –Lanes: x2, x4, x8, x16 –Support for all protocols CXL.cache/ mem/io or only CXL.cache/mem
  • CXL.cache/mem –Containment and skid modes –Early MAC termination
  • Optimized for area, performance & latency
  • PCRC calculation & validation
  • Efficient key control & refresh
  • Bypass mode

Applications

  • Cloud Computing
  • AI/Deep Learning, Media/Graphics
  • Memory Expansion
  • General Purpose Acceleration

Deliverables

  • Synthesizable RTL developed in compliance with the IEEE1364 Verilog-2005 standard
  • Verilog integration testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Databook
  • Hardware user guide
  • Hardware installation guide

Technical Specifications

Maturity
Available on request
Availability
Available
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Semiconductor IP