CXL 2.0 Integrity and Data Encryption Security Module

Overview

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiting high performance, heterogeneous computing for data-intensive workloads.
The Synopsys CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP) in the case of CXL.io. The Security Module is compliant with the IDE specification as defined for CXL 2.0 which also references PCI Express IDE specification
for the CXL.io protocol. The Synopsys CXL 2.0 IDE Security Module integrates seamlessly with the Synopsys CXL controllers to accelerate SoC integration.

Benefits

Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
Compliant with PCI Express IDE specification for CXL.io
High-performance AES-GCM based packet encryption, decryption, authentication
Seamless integration with Synopsys DesignWare controller IP
Supports CXL 2.0 data rates
Customer configurable
CXL.cache/mem
Support for TDISP
Optimized for area, performance & latency
Multi-stream support
PCRC calculation & validation
Efficient key control & refresh
Bypass mode

Applications

Cloud computing
AI/Deep Learning, Media/Graphics
Memory expansion
General purpose acceleration

Deliverables

Synthesizable RTL developed in compliance with the IEEE1364 Verilog-2005 standard
Verilog integration testbench
Sample synthesis script and constraints
Sample simulation script
Databook
Hardware user guide
Hardware installation guide

Technical Specifications

Maturity

Available on request

Availability

Available

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