The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be configured for dual-mode applications supporting runtime-selectability between device and host mode. The configurable and scalable IP supports all key required features of the CXL 3.x specification and full backward compatibility with CXL 2.0, 1.0 and 1.1 specifications. The IP also supports PCI Express 6.x, 5.0, 4.0, and 3.1 specifications, and can be easily connected to a 64GT/s PHY through the built-in PIPE 6.x interface. The CXL controller supports the MultiStream architecture, offering multiple application interfaces for maximum throughput efficiency across various link widths and payloads. The high-quality, synthesizable IP is optimized for maximum throughput and minimum latency in a 64GT/s x16 configuration, but can be configured to support CXL port bifurcation and degraded modes, as well as all 3 defined CXL device types for maximum application flexibility. The CXL Controller IP integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interfaces or industry standard AMBA interfaces, with conservative timing suitable for a wide range of ASIC and FPGA technologies.
The Integrity and Data Encryption (IDE) Security Modules for CXL 2.0 and the IDE Security Modules for CXL 3.x are standards-compliant and pre-verified with the Controller IP to help designers protect data transfer in their SoCs against tampering and physical attacks. The security modules meet the required high bandwidth with optimal area and latency as low as zero cycles for CXL.cache/.mem protocols in skid mode. The CXL Controllers with IDE security IP module support TEE Device Interface Security Protocol (TDISP) for CXL.io protocol released by PCI-SIG. TDISP standardized framework defines how to secure the interconnect between virtual machine hosts and devices, regardless of where the data center resides or who has access to the servers inside. The CXL Controllers with IDE enable designers to build full TDISP support in their hyperscale SoCs and mitigate against data and system attacks, addressing the challenges of secure I/O virtualization. Learn about the broad portfolio of Security Solutions for Interfaces.
The CXL Controller IP is based on the PCI Express controller IP which has been silicon validated in over 1800 designs with multiple hardware platforms, PHYs, and PCI Express verification suites, thereby reducing risk and accelerating time-to-market.
