CXL 2.0 Dual Mode Controller

Overview

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards.
CXL cards has same form factor as PCIE , and can be used in same pcie slot.
Primesoc CXL controller cores can work in PCIE mode only(when auto negotiation fails) OR CXL mode having pcie transfers handled as IO flits, along with Cache and Mem transfers.

Key Features

Compatible with CXL 2.0 specification and backward compatible with CXL V1.0 and CXL V1.1
Supports G3,G4,G5 speed rates when working at CXL mode, and supports G1,G2,G3,G4,G5 modes when working at PCIE mode.
Core can be configured to work as Host or as Device.
X1/X2/X4/X8/X16 configurable lanes.
Core comes with Inhouse BFM tested.
CXL.io,CXL.cache,CXL.mem modes supported and user can select from these modes to get optimised gatecount.
32bit or 64bit Flexbus interface when working in CXL mode and 32 ot 64bit PIPE interface when working in PCIE mode.
16bit PIPE interface supported as wrapper code.
Native TLP interface/AXI without DMA/AXI with DMA modes supported when working in PCIE mode.
Intel defined SFI interface for cxl.io , CPI interface for cxl.cache/mem modes supported.
Amba's CXS-B protocol supported for cxl cache/mem modes.
AXI4 Master/AXI4 slave supported.
AXI4 master lite/AXI4 slave lite supported.
Plug and Play CXL/PCIE soft IP cores with ready to use interfaces for Memory mapped applications and NIC applications.
Soft IP cores are technology independent and can be used with FPGA/ASIC implementations.

Benefits

Easy to use plug and play Soft IP digital controller cores.

Applications

NIC
Memory
Accelerators
AI
Machine learning

Deliverables

RTL Code in verilog.
Documentations for design and verification
Lint/synthesis scripts
Inhouse developed , unlimited licenses of Verification environment in system verilog/UVM
FPGA netlist/bitfiles

Technical Specifications

Foundry, Node

Any Node

Maturity

FPGA proven

Availability

Immediate

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