CSI2 RX; Camera Serial Interface, MIPI Compliant

Overview

The CSI2 Receiver IP Interfaces between Camera module which has the transmitter and the application processor. The CSI2 Receiver IP is fully compliant with the MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2) Version 1.1 and D-PHY Version 1.1. The CSI2 Receiver IP supports flexible pixel interface where based on the data format the pixels are transferred to the application interface.

Key Features

Supports up to 4-Data lanes
The Data lanes can be programmed to operate at 1 or 2 or 3 or 4 lanes
Each Data lane supports up to 1.5Gbps at High Speed mode and up to 20-MHz at Low power mode
Supports 4-virtual channel
Supports Camera control Interface for controlling the CSI2 Transmitter

Two wire, Bi directional and half duplex interface (SCLK, SDA), Supports 400KHz and 7-bit Slave addressing

Supports ECC -single bit Error correction and double bit error detection for packet headers
Supports CRC error checking for the payload
Supports the following error handling mechanism

D-PHY Layer Errors
ECC and CRC Errors
Frame Sync Errors
Invalid Data format

Supports High speed data, Ultra Low power (Escape mode) control and Low power data modes of operations

Block Diagram

Deliverables

Source Code – Verilog HDL
Verification Environment
Synthesis Scripts
Timing Constraints
User Manual

Technical Specifications

Availability

Now

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