Cryptographic Cores IP

Overview

Lightweight, Scalable Cryptographic Accelerators for Secure SoC Designs

The Cryptographic Cores IP portfolio delivers secure, high-performance implementations of symmetric, asymmetric, and post-quantum algorithms. Designed for low-area, low-latency operation, the silicon-proven cores help SoC designers and embedded teams build trusted, efficient devices for IoT, automotive, medical, and industrial markets.

AES Encryption

Supports 128-, 192-, and 256-bit keys with ECB, CBC, GCM, OFB, and CTR modes. Configurable for optimal performance/power trade-offs.

Ascon for Lightweight Use Cases

Authenticated encryption and hashing based on the NIST SP800-232 finalist. Compact and efficient, ideal for small-footprint devices.

Elliptic Curve Cryptography (ECC)

Implements ECDSA and ECDH for secure identity, authentication, and encryption, optimized for embedded systems.

Post-Quantum Cryptography (PQC)

Hardware acceleration for ML-KEM (Kyber), ML-DSA (Dilithium), and SLH-DSA (SPHINCS+) — ready for emerging quantum-safe mandates.

Secure Hashing

SHA-2 and SHA-3 cores with integrated countermeasures provide fast, secure integrity and signature verification.

Key Lifecycle Support

On-chip TRNG-based key generation with integrated management for generation, rotation, and revocation.

Key Features

  • Full Algorithm Coverage: AES, SHA, ECC, Ascon, and PQC options. All hardened and production-ready
  • Side-Channel Resistance: Built-in defences against side-channel and fault injection attacks as standard
  • Flexible Integration: Configurable for silicon area, latency, and interface options (AXI, APB, etc.)
  • Post-Quantum Ready: Support for Kyber, Dilithium, and SPHINCS+ ensures future-proof security
  • Standards Compliant: FIPS 186-4 and ISO/IEC 14888 conformant, with support for certification workflows
  • Low Power, High Throughput: Designed to meet the demands of constrained IoT devices and real-time systems

Benefits

  • SoC & ASIC Design Teams: Build secure chips with certified crypto IP that meets performance and area goals.
  • Embedded Platform & Security Architects: Choose from proven cores to enforce secure boot, identity, and encryption policies.
  • Embedded Designers: Integrate crypto acceleration into MCU or subsystem with minimal code overhead.
  • Compliance & QA: Achieve regulatory compliance faster with certifiable, standards-aligned building blocks.

Deliverables

  • RTL,
  • test benches,
  • LEF/GDSII,
  • SystemVerilog models,
  • synthesis constraints,
  • documentation

Technical Specifications

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Semiconductor IP