The Core Powered Wide Range PLL is easy to integrate, requiring no analog power supply, and can be placed anywhere on a chip.
This Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. These PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and thick-oxide devices, on a core level power supply.
PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 7 600 MHz Post-Divide Reference frequency FPFD 7 200 MHz VCO Frequency FVCO 5000 10000 MHz Output Frequency FOUT 7 5000 MHz Lock Time TLOCK 70 µs Reset Time tRESET 1 µs Output Duty Cycle tDO 47 53 % Area A 0.033 sq. mm Total Power IDD 19 mW Operational Voltage V 0.675 0.75 0.825 V Operational Temperature TOP -40 25 125 O C Table 1: PLL Operational Range
