Core Powered FracN/SSCG PLL on TSMC CLN4P

Overview

The Core Powered Fractional-N / Spread Spectrum PLL is an easy to integrate macro, requiring no analog power supply, and can be placed anywhere on a chip.

This Fractional-N /Spread Spectrum PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, and clock tracking for fine tuning on-the-fly. The PLLs are designed for digitallogic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.

The programmable Fractional-N divider allows the PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. “On the fly” capability means the frequency transition and re-obtaining lock process for small frequency adjustment is glitch free and contains limited frequency over/undershoot.

Furthermore, itis a requirement by the FCC and equivalent international bodies that electronic devices including game-consoles, PCs, and high speed compute servers, limit Electromagnetic Interference (EMI) when they operate. The Spread Spectrum function of the PLL is capable of generating precise clock spreads (using a triangular modulation profile) that help reduce EMI. Programmable options allow the user to control the degree of spread in fine steps of modulation frequency and depth.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and thick-oxide (1.2V and 1.2V-OD-1.5V) devices operated on a core voltage level power supply.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 5 600 MHz Post-Divide Reference Frequency (Integer mode) FPFD 5 200 MHz Post-Divide Reference Frequency (Frac/SS mode) FPFD 5 7.5 MHz VCO Frequency FVCO 8000 MHz Output Frequency FOUT 7.5 4000 MHz Output Duty Cycle tDO 45 55 % Area A 0.033 sq. mm Total Power IDD 16.7 mW Operational Voltage VDIG 0.675 0.75 0.825 V Operational Temperature TOP -40 25 125 C

Key Features

  • Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
  • Entirely core voltage powered, needs no analog supply voltage
  • Wide Ranges of Input and Output Frequency for diverse clocking needs
  • Very fine precision: near 1 part per billion resolution
  • Fully integrated 32-bit datapath (8-bit integer plus 24-bit fractional)
  • Ability to generate precise system clocks synchronized to track remote sources
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Small area footprint
  • Excellent jitter performance with optimized noise rejection

Block Diagram

Core Powered FracN/SSCG PLL on TSMC CLN4P Block Diagram

Technical Specifications

Foundry, Node
TSMC CLN4P
TSMC
Pre-Silicon: 4nm
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Semiconductor IP